In one type of circuit element or device, hereinafter "tunneling device," electrons are caused to "tunnel" from a first conductor to a second conductor through an insulating dielectric separating the first and second conductors from each other. This effect is termed the Fowler-Nordheim field emission of electrons. This field emission of electrons occurs in response to a voltage difference across the dielectric by means of the application of different voltages to each conductor. When this voltage difference exceeds a threshold voltage, the Fowler-Nordheim field emission or tunneling of electrons is induced in the dielectric.
The tunneling device constitutes an unknown impedance to the applied voltage. When the voltage applied is less than the tunneling device's threshold voltage, the device acts primarily as a capacitive impedance, with charge build-up occurring at the junction between each conductor and the dielectric. However, when the threshold voltage is exceeded, the tunneling electrons induce a current through the dielectric. Thus, above the threshold voltage, the input impedance of the tunneling device also has a resistive component.
Each time an electron tunneling current is induced through the tunneling device, some of the electrons become trapped in the dielectric. As the level of trapped electrons in the dielectric increases, the threshold voltage which must be applied across the tunneling device to induce the electron tunneling current in the dielectric also increases.
In the prior art, it is common practice to apply a voltage to the tunneling device which exceeds the threshold voltage by a margin sufficient to ensure that the applied voltage will always exceed the increasing threshold voltage over the life expectancy of the tunneling device. It is to be noted that the life expectancy of a tunneling device is determined by the total amount of charge that can be passed through the dielectric before the dielectric breaks down.
A significant disadvantage and limitation of selecting a margin by which the applied voltage will exceed the threshold voltage is that, should the margin selected be either too small or too large, the number of times or cycles the tunneling device will be operable is reduced. If the margin is too small, the threshold voltage will over time approach the applied voltage such that tunneling of electrons will not occur across the dielectric. In a circuit utilizing the tunneling device, this condition will cause an operational fault. Conversely, if the margin is too large, the current density through the tunneling device will be excessive early in the expected life of the tunneling device. Since the life expectancy of the tunneling device is related to the total amount of charge that has passed through the dielectric, initial excessive current densities will cause the total charge level to be reached in fewer cycles than if the margin is optimally selected.
However, the optimal selection of the margin by which the applied voltage exceeds the threshold voltage is difficult to achieve in integrated circuits which have a tunneling device. Processing variations in the thickness of dielectric and in the amount of overlap of the first and second conductors to each other will cause the threshold voltage of the tunneling device to vary between each integrated circuit.
An electrically erasable, programmable read only memory (EEPROM) and a nonvolatile random access memory (NOVRAM) are examples of integrated circuits which have tunneling devices. In each of these memories, there is a plurality of nonvolatile memory cells. In each cell, a polysilicon floating gate is totally surrounded by a dielectric, so that the charge state of the floating gate remains undisturbed for very long periods of time in the absence of outside influences. The charge level on the floating gate, i.e., the presence or absence of excess electrons, is used to represent the storage of either binary state. Charge is applied to and removed from the floating gate through a programming tunneling region and an erase tunneling region, respectively, which are formed in the dielectric surrounding the floating gate. The position of each of these tunneling regions is defined by a separate polysilicon layer which is positioned such that it overlaps a portion of the floating gate and is spaced from the floating gate a selected distance by the dielectric.
In one embodiment of the floating gate cell, electrons are introduced onto the floating gate, in a "write" mode as follows. A low potential is applied to a programming electrode disposed adjacent to the dielectric forming the programming tunneling regions and capacitively coupled to the floating gate. The high potential is applied to a bias electrode. The bias electrode is capacitively coupled to the floating gate such that the potential of the floating gate is elevated to the high potential. Therefore, a potential difference exists over the programming tunneling region. The low and high potentials are selected so that this potential difference exceeds the tunneling threshold of the programming region so that electrons are introduced onto the floating gate.
Similarly, electrons are removed from the floating gate, in a "erase" mode, as follows. An erase electrode is disposed adjacent to the erase tunneling region and capacitively coupled to the floating gate. A low potential is applied to the bias electrode such that by capacitive coupling, the floating gate is maintained at such low potential. Upon application of a sufficiently high potential to the erase electrode, a potential difference will be developed across the erase tunneling region which exceeds the tunneling threshold voltage. Electrons will then be removed from the floating gate to the erase electrode.
As described hereinabove, the voltage required to erase or program the floating gate tends to increase as a function of the number of programming or erase cycles of the floating gate because of trapped electrons in the dielectric. In the prior art, the high potential used to induce tunneling was selected to be much higher than desirable initially in the life of the nonvolatile memory cell. Even after the cell has been cycled many times, the high potential would still cause the voltage across the tunneling regions to exceed the threshold voltage required to adequately erase or program the floating gate.
The maximum number of erase/program cycles, i.e., the endurance of a nonvolatile memory cell, is directly related to the total charge that can be passed through the erase and program tunneling regions. Decreasing the current density or the rate at which the charge is passed through these tunneling regions increases the number of erase/program cycles possible in a given cell. Consequently, applying a higher than necessary voltage initially to the tunneling regions in a nonvolatile memory cell produces a higher than necessary current density in the tunneling region during the first cycles, thereby significantly reducing the endurance of the nonvolatile memory cell.
In nonvolatile integrated circuit memory devices as described above, the high potential applied to each cell to induce tunneling is generated "on-chip" from the normal 5 volt logic level voltage input to the chip. Because of processing variations between chips, the level of this high potential is not readily controlled to a degree required to optimize the voltage and current densities in the tunneling regions. These processing variations render the input impedance of each tunneling device to be relatively unknown, in addition to being non-linear. Also, because of mismatches between each tunneling region on the same chip, the on-chip generated high potential cannot be optimized for each region. Furthermore, the polysilicon layer forming part of the erase tunneling device in each memory cell may be common to several cells to form, for example, a word line. Thus, the on-chip generated high potential cannot be satisfactorily optimized for all these variations.